This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
The data valid window is defined as the stable data capture window by a clock at a first set of flip-flops at a receiver. As system interface performances continue to grow, the size of the data valid window for high-speed I/O interfaces available at customers' final products continues to shrink. This is especially true for high-speed memory interfaces like DDR3, LPDDR2, LPDDR3, and DDR4.
Before customers close the design of a system prior to high-volume production, there is a need to measure and monitor the data valid window of the system. Traditionally, this testing is performed on a small number of chip samples, which may result in problems being missed.